TECHNICAL BULLETIN COPYRIGHT 1992 _______________________ TANDY COMPUTER PRODUCTS ______________________ DATE: March 22, 1983 REVISION DATE: March 22, 1983 BULLETIN NO: I:15 PRODUCT: 26-1003 4K RAM Model I 26-1006 16K RAM Model I SUBASSEMBLY: AXX-1002 PCB XRX-III Cassette Modification SUBASSEMBLY REVISION: All Revisions ______________________________________________________________________________ PURPOSE: XRX-III Cassette modification instructions. ______________________________________________________________________________ DISCUSSION: The early Model I computers had a timing problem in the cassette operation causing the volume setting on the recorder to be very critical. The XRX-III (Cload Mod) corrects this problem allowing a broader range of volume settings. This modification should only be done to the Model I computers with the early version ROM chips. The later version ROM's have the timing correction built in. The ROM's can be identified by their power response. EARLY ROM LATE ROM MEMORY SIZE ? MEM SIZE ? RADIO SHACK LEVEL II BASIC R/S L2 BASIC Refer to Figures 2 and 3 for the following discussion. The XRX-III cassette modification works on the theory of re-setting the R/S Latch, Z24, just as the OUTSIG* line would do, but before the OUTSIG* line does. In this manner, we allow for a stretched audio CASSIN signal (due to poor cassette motor speed control and high-volume stretching) and use only the edge trigger level of the CASSIN signal bit. The remaining stretched CASSIN signal is totally ignored by the CPU's test bit signal at Z44, Pin 15. As bits are entered from the tape into the TRS-80 cassette interface, precise timing of these input bits is essential. The CPU must determine the bit time, and if there was a logical "0" or a logical "1" during that bit time. Each bit time is measured in milliseconds. The rate at which the information is transferred is faster in Level II (500 baud, or 2ms bit time) than in Level I (250 baud, or 4ms bit time). Regardless of whether you are in Level I or Level II, each data pulse from the cassette will measure approximately 200 us under optimum equipment operating conditions. _____________________________________________________________________________ Proprietary Information TB I:15 Tandy Corporation PAGE 1 OF 4 TECHNICAL BULLETIN COPYRIGHT 1992 _______________________ TANDY COMPUTER PRODUCTS ______________________ It is these cassette data pulses that are likely to stretch out to 600us. When these pulses are in the range of 500 to 650us, there is great risk that the CPU will recognize this as a second pulse because it is close enough to the next window time. The XRX-III is essentially a controlled inhibit signal used to halt stretched waveforms and thereby increase loading volume levels. ZA1 is dual functional. Pins 1, 2, 3, 4, 5 and 6 form a control gate with an inverted output that controls the amount of cassette pulse that is used for setting bits into the CPU. Normally, pin 2 will be at a logical low. When the first cassette pulse is received by ZA1, pin 1; ZA1, pin 4 will output a negative going pulse which is detected by the R/S Latch, Z24, pin 4. This sets the R/S Latch. Z24, pin 8 will go high and Z24, pin 11 will go low. Z24, pin 8 is used to set the R/S Latch contained in ZA1. This R/S Latch is the second function of ZA1 and is formed by pins 8, 9, 10, 11, 12 and 13. When ZA1, pin 11 goes high, ZA1, pin 10 goes low. ZA1, pin 11 is used to inhibit the gate at ZA1, pin 2. This causes ZA1, pin 4 to go back high and remain high until ZA1, pin 2 goes low again. Information is passed through gate ZA1, pin 4 only when ZA1, pin 2 is low. Control of the amount of time that ZA1, pin 2 stays high is performed by ZA2. ZA2 is a 12-bit Binary Counter. Because of the high stability required by the timing circuit, a highly stable clock input to ZA2, pin 10 is used. The clock input to ZA2 comes from the TRS-80 on-board Video section, Z65, pin 1. ZA2 starts counting from the time that ZA1, pin 10 goes low. This start time will follow the first cassette pulse in by approximately 110ns which is the propagation time that is allowed for getting the pulse to the counter. At this time, ZA2 will count 640 pulses of the 887 KHz clock (which, when converted, equals 721us) before resetting R/S Latch ZA1. This cause ZA1, pin 2 to return low, allowing another cassette pulse to be transmitted through gate ZA1. This set/reset cycle continues for each cassette pulse (refer to the TRS-80 schematic for additional information). PROCEDURE: Refer to Figure 1 for the following procedures. 1. Place the modification PCB on the trace side in the upper right corner of the Model I Logic PCB. 2. Carefully cut the foil pattern between Z24, Pin 9 and Z4, Pin 10. 3. Connect the Red wire to Z25, Pin 14 (+5 volts). _____________________________________________________________________________ Proprietary Information TB I:15 Tandy Corporation PAGE 2 OF 4 TECHNICAL BULLETIN COPYRIGHT 1992 _______________________ TANDY COMPUTER PRODUCTS ______________________ 4. Connect the Black wire to Z4, Pin 7 (ground). 5. Connect the Yellow wire to Z43, Pin 9. 6. Connect the Green wire to Z4, Pin 10. 7. Connect the Blue wire to Z24, Pin 12. 8. Connect the Violet wire to Z24, Pin 9. 9. Check all solder connections and then check the operation with CSAVE and CLOAD. Figure 1. TRS-80 Microcomputer PCB, Bottom Side (Partial View). _____________________________________________________________________________ Proprietary Information TB I:15 Tandy Corporation PAGE 3 OF 4 TECHNICAL BULLETIN COPYRIGHT 1992 _______________________ TANDY COMPUTER PRODUCTS ______________________ Figure 2. XRX-III Modification Schematic. Figure 3. Timing Diagram. _____________________________________________________________________________ Proprietary Information TB I:15 Tandy Corporation PAGE 4 OF 4